MT40A1G16WBU-083E:B TR

16Gb: x16 TwinDie Single Rank DDR4 SDRAM Description TwinDie™ 1.2V DDR4 SDRAM MT40A1G16 – 64 Meg x 16 x 16 Banks x 1 Ranks Description Options The 16Gb (TwinDie™) DDR4 SDRAM uses Micron’s 8Gb DDR4 SDRAM die; two x8s combined to make one x16. Similar signals as mono x16, there is one extra ZQ connection for faster ZQ Calibration and a BG1 control required for x8 addressing. Refer to Micron’s 8Gb DDR4 SDRAM data sheet (x8 option) for the specifications not included in this document. Specifications for base part number MT40A1G8 correlate to TwinDie manufacturing part number MT40A1G16. Features • • • • • • • Marking • Configuration – 64 Meg x 16 x 16 banks x 1 rank • 96-ball FBGA package (Pb-free) – 9.5mm x 14mm x 1.2mm Die Rev :A – 8.0mm x 14mm x 1.2mm Die Rev :B, D – 7.5mm x 13.5mm x 1.2mm Die Rev :E • Timing – cycle time1 – 0.625ns @ CL = 22 (DDR4-3200) – 0.682ns @ CL = 21 (DDR4-2933) – 0.750ns @ CL = 19 (DDR4-2666) – 0.750ns @ CL = 18 (DDR4-2666) – 0.833ns @ CL = 17(DDR4-2400) – 0.833ns @ CL = 16 (DDR4-2400) – 0.937ns @ CL = 15 (DDR4-2133) – 1.071ns @ CL = 13 (DDR4-1866) • Self refresh – Standard • Operating temperature – Commercial (0°C ≤ T C ≤ 95°C) • Revision Uses two x8 8Gb Micron die to make one x16 Single rank TwinDie VDD = V DDQ = 1.2V (1.14–1.26V) 1.2V V DDQ-terminated I/O JEDEC-standard ball-out Low-profile package TC of 0°C to 95°C – 0°C to 85°C: 8192 refresh cycles in 64ms – 85°C to 95°C: 8192 refresh cycles in 32ms Note: 1G16 HBA WBU KNR -062E -068 -075 -075E -083 -083E -093E -107E None None :A :B, D :E 1. CL = CAS (READ) latency. Table 1: Key Timing Parameters Speed Grade1 Data Rate (MT/s) Target tRCD-tRP-CL -062Y 3200 22-22-22 -062E 3200 22-22-22 13.75 13.75 13.75 -068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75) -075E 2666 18-18-18 13.50 13.50 13.50 -075 2666 19-19-19 14.25 14.25 14.25 -083E 2400 16-16-16 13.32 13.32 13.32 -083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75) -093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50) -093 2133 16-16-16 15.00 15.00 15.00 -107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50) Note: tRCD (ns) 13.75 (13.32) tRP (ns) 13.75 (13.32) CL (ns) 13.75 (13.32) 1. Refer to Speed Bin Tables for additional details. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Description Table 2: Addressing Parameter 1024 Meg x 16 Configuration 64 Meg x 16 x 16 banks x 1 rank Bank group address BG[1:0] Bank count per group 4 Bank address in bank group BA[1:0] Row addressing 64K (A[15:0]) Column addressing 1K (A[9:0]) Page size Note: 1KB 1. Page size is per bank, calculated as follows: Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Ball Assignments Ball Assignments Figure 1: 96-Ball x16 SR DDP Ball Assignments 1 2 3 4 5 6 7 8 9 VDDQ VSSQ UDQ0 VPP VSS VDD UDQS_t UDQ1 VDD VDDQ UDQ4 UDQ2 UDQ3 UDQ5 VSSQ VDD VSSQ UDQ6 UDQ7 VSSQ VDDQ VSS NF/UDM_n/ UDBI_n VSSQ NF/LDM_n/ LDBI_n VSSQ UZQ VSSQ VDDQ LDQS_c LDQ1 VDDQ LZQ VDDQ LDQ0 LDQS_t VDD VSS VDDQ VSSQ LDQ4 LDQ2 LDQ3 LDQ5 VSSQ VDD VDDQ LDQ6 LDQ7 VDDQ VDD A A UDQS_c VSSQ VDDQ B B C C D D E E F F G G H H J J K K VSS CKE CK_t ODT CK_c VSS L L VDD WE_n/A14 ACT_n CS_n RAS_n/A16 VDD M M VREFCA BG0 A10/AP A12/BC_n CAS-n/A15 BG1 VSS BA0 A4 A3 BA1 TEN A0 A1 A5 ALERT_n N N P P RESET_n A6 R R VDD A8 A2 A9 A7 VPP VSS A11 PAR VSS A13 VDD T Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN T 1. See Ball Descriptions in the monolithic data sheet. 2. A slash “/” defines a selectable function. For example: Ball E2 = NF/UDM_n/UDBI_n where either NF, UDM_n, or UDBI_n is defined via MRS. 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram (128 Meg x 16 x 16 Banks x 1 Rank) (128 Meg x 16 x 16 banks) Byte 1 (64 Meg x 8 x 16 banks) Byte 0 (64 Meg x 8 x 16 banks) UDM_n/ UDBI_n UDQ[7:0] UDQS_t UDQS_c UZQ CS_n RAS_n/A16 CAS_n/A15 WE_n/A14 ACT_n CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN CK_t BG[1:0] BA[1:0] A[13:0] PAR VrefCA 5 CK_c CKE ODT TEN RESET_n ALERT_n LZQ LDM_n/ LDBI_n LDQ[7:0] LDQS_t LDQS_c Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Connectivity Test Mode Connectivity Test Mode Connectivity test (CT) mode for the x16 TwinDie single rank (SR) device is the same as two mono x8 devices connected in parallel. The mapping is restated for clarity. Minimum Terms Definition for Logic Equations The test input and output pins are related by the following equations, where INV denotes a logical inversion operation and XOR a logical exclusive OR operation: MT0 = XOR (A1, A6, PAR) MT1 = XOR (A8, ALERT_n, A9) MT2 = XOR (A2, A5, A13) MT3 = XOR (A0, A7, A11) MT4 = XOR (CK_c, ODT, CAS_n/A15) MT5 = XOR (CKE, RAS_n/A16, A10/AP) MT6 = XOR (ACT_n, A4, BA1) MT7L = XOR (BG1, LDM_n/LDBI_n, CK_t) MT7U = XOR (BG1, UDM_n/UDBI_n, CK_t) MT8 = XOR (WE_n/A14, A12 / BC, BA0) MT9 = XOR (BG0, A3, RESET_n and TEN) Logic Equations for a x16 TwinDie, SR Device Byte 0 LDQ0 = MT0 LDQ1 = MT1 LDQ2 = MT2 LDQ3 = MT3 LDQ4 = MT4 LDQ5 = MT5 LDQ6 = MT6 LDQ7 = MT7L LDQS_t = MT8 LDQS_c = MT9 Byte 1 UDQ0 = MT0 UDQ1 = MT1 UDQ2 = MT2 UDQ3 = MT3 UDQ4 = MT4 UDQ5 = MT5 UDQ6 = MT6 UDQ7 = MT7U UDQS_t = MT8 UDQS_c = MT9 x16 TwinDie, SR Internal Connections The figure below shows the internal connections of the x16 TwinDie, SR. The diagram shows why byte 0 and byte 1 outputs have the same logic equations except LDQ7 and UDQ7; they are different because the DM_n/DBI_n pins are not common for each byte. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Connectivity Test Mode Figure 3: x16 TwinDie, SR Byte 1 Byte 0 UDM_n/ UDBI_n UZQ UDQ[7:0] UDQS_t UDQS_c CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN CS_n RAS_n/A16 CK_t BG[1:0] BA[1:0] A[13:0] CAS_n/A15 WE_n/A14 ACT_n PAR VREFCA 7 CK_c CKE ODT TEN RESET_n ALERT_n LZQ LDM_n/ LDBI_n LDQ[7:0] LDQS_t LDQS_c Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Electrical Specifications – Leakages Electrical Specifications – Leakages Table 3: Input and Output Leakages Symbol Parameter Min Max Units Notes II Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) –4 4 µA 1 IVREF VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) –4 4 µA 2 IZQ Input leakage on ZQ pin –50 10 µA ITEN Input leakage on TEN pin –12 20 µA IOZPD Output leakage: VOUT = VDDQ – 10 µA 3 IOZPU Output leakage: VOUT = VSSQ –50 – µA 3, 4 Notes: 1. 2. 3. 4. Any input 0V < Vin < 1.1V VREFCA = VDD/2, VDD at valid level. DQs are disabled. ODT is disabled with the ODT input HIGH. Temperature and Thermal Impedance It is imperative that the DDR4 SDRAM device’s temperature specifications, shown in the following table, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances listed in Table 5 (page 9) apply to the current die revision and packages. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the thermal impedance table. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. The DDR4 SDRAM device’s safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Electrical Specifications – Leakages Table 4: Thermal Characteristics Notes 1–3 apply to entire table Parameter Operating temperature Notes: Symbol Value Units TC 0 to 85 °C 0 to 95 °C Notes 4 1. MAX operating case temperature TC is measured in the center of the package, as shown below. 2. A thermal solution must be designed to ensure that the device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if available, must be enabled. Figure 4: Temperature Test Point Location Test point Length (L) 0.5 (L) 0.5 (W) Width (W) Table 5: Thermal Impedance Die Rev. A B, D E Substrate conductivity Θ JA (°C/W) Airflow = 0m/s Θ JA (°C/W) Airflow = 1m/s Θ JA (°C/W) Airflow = 2m/s Θ JB (°C/W) Θ JC (°C/W) Low TBD TBD TBD N/A TBD High TBD TBD TBD TBD N/A Low 43.9 33.0 29.5 N/A 3.3 High 27.1 21.7 20.1 10.5 N/A Low TBD TBD TBD N/A TBD High TBD TBD TBD TBD N/A Note: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN Notes 1 1 1 1. Thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM DRAM Package Electrical Specifications DRAM Package Electrical Specifications Table 6: DRAM Package Electrical Specifications for x16 Devices Notes 1–4 apply to the entire table DDR4-1600, -1866 DDR4-2133, -2400 DDR4-2666, -2933 Parameter Input/ output Zpkg Package delay Lpkg DQSL_t/ DQSL_c/ DQSU_t/ DQSU_c DQSL_t/ DQSL_c, DQSU_t/ DQSU_c, Input CTRL pins Input CMD ADD pins CK_t, CK_c Min Max Min Max Min Max Unit Notes ZIO 30 50 30 50 30 50 ohm 5, 6 TdIO 60 120 60 120 60 120 ps 6,7 LIO – 5.0 – 5.0 – 5.0 nH Cpkg CIO – 3.0 – 3.0 – 3.0 pF Zpkg ZIO DQS 30 50 30 50 30 50 ohm 5 TdIO DQS 60 120 60 120 60 120 ps 7 LIO DQS – 5.0 – 5.0 – 5.0 nH Package delay Lpkg Cpkg CIO DQS – 3.0 – 3.0 – 3.0 pF Delta Zpkg DZIO DQS – 20 – 20 – 20 ohm 5, 8 Delta delay DTdIO DQS – 45 – 45 – 45 ps 7, 8 ZI CTRL 35 65 35 65 35 65 ohm 5, 9 TdI CTRL 75 120 75 120 75 120 ps 7, 9 Zpkg Package delay Lpkg LI CTRL – 6.5 – 6.5 – 6.5 nH Cpkg CI CTRL – 2.5 – 2.5 – 2.5 pF Zpkg ZI ADD CMD 35 65 35 65 35 65 ohm 5, 10 TdI ADD CMD 70 125 70 125 70 125 ps 7, 10 Lpkg LI ADD CMD – 6.5 – 6.5 – 6.5 nH Cpkg CI ADD CMD – 3.0 – 3.0 – 3.0 pF Zpkg ZCK 30 55 30 55 30 55 ohm 5 TdCK 80 135 80 135 80 135 ps 7 Package delay Package delay Input CLK Symbol Delta Zpkg DZDCK – 0.5 – 0.5 – 0.5 ohm 5, 11 Delta delay DTdDCK – 1.2 – 1.2 – 1.2 ps 7, 11 Lpkg LI CLK – 6.0 – 6.0 – 6.0 nH Cpkg CI CLK – 3.0 – 3.0 – 3.0 pF ZQ Zpkg ZO ZQ – 40 – 40 – 40 ohm 5 ZQ delay TdO ZQ 30 135 30 135 30 135 ps 7 ALERT Zpkg ZO ALERT 30 55 30 55 30 55 ohm 5 ALERT delay TdO ALERT 65 110 65 110 65 110 ps 7 Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1. The package parasitic (L and C) are not subject to production testing. If the package parasitic (L and C) are measured, the capacitance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side. 2. Package implementations should satisfy targets if the Zpkg and package delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM DRAM Package Electrical Specifications 3. 4. 5. 6. 7. 8. 9. 10. 11. values shown. The package design targets are provided for reference, system signal simulations should not use these values but use the Micron package model. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg). ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg). Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td). ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td). Table 7: Pad Input/Output Capacitance DDR4-1600, -1866, -2133 Parameter DDR4-2400, -2666 DDR4-2933 Symbol Min Max Min Max Min Max Unit Notes Input/output capacitance: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c CIO 1.8 2.8 1.8 2.8 1.8 2.8 pF 1, 2, 3 Input capacitance: CK_t and CK_c CCK 2.1 2.9 2.1 2.9 2.1 2.9 pF 1, 2, 3, 4 Input capacitance delta: CK_t and CK_c CDCK 0 0.05 0 0.05 0 0.05 pF 1, 2, 3, 5 Input/output capacitance delta: DQS_t and DQS_c CDDQS 0 0.05 0 0.05 0 0.05 pF 1, 3 CI 1.6 2.6 1.6 2.6 1.6 2.6 pF 1, 3, 6 Input capacitance delta: All CTRL input-only pins CDI_CTRL –0 .9 0.9 –0 .9 0.9 –0 .9 0.9 pF 1, 3, 7 Input capacitance delta: All ADD/CMD input-only pins CDI_ADD_CMD –0 .9 0.9 –0 .9 0.9 –0 .9 0.9 pF 1, 3, 8, 9 CDIO –0.16 0.16 –0.16 0.16 –0.16 0.16 pF 1, 2, 10, 11 CALERT 1.1 2.3 1.1 2.3 1.1 2.3 pF 1, 3 Input/output capacitance: ZQ pin CZQ – 3.7 – 3.7 – 3.7 pF 1, 3, 12 Input/output capacitance: TEN pin CTEN 0.2 2.3 0.2 2.3 0.2 2.3 pF 1, 3, 13 Input capacitance: CTRL, ADD, CMD input-only pins Input/output capacitance delta: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c Input/output capacitance: ALERT pin Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading matches DQ and DQS. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM DRAM Package Electrical Specifications 2. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these values but use the Micron package model. The capacitance, if and when, is measured according to the JEP147 specification, “Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA),” with VDD, VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD = VDDQ = 1.5V, VBIAS = VDD/2 and on-die termination off. 3. This parameter applies to SR x16 TwinDie, obtained by de-embedding the package L and C parasitics. 4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)). 5. Absolute value of CIO (DQS_t), CIO (DQS_c) 6. Absolute value of CCK_t, CCK_c 7. CI applies to ODT, CS_n, CKE, A[15:0], BA[1:0], RAS_n, CAS_n, and WE_n. 8. CDI_CTRL applies to ODT, CS_n, and CKE. 9. CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)). 10. CDI_ADD_CMD applies to A[15:0], BA1:0], RAS_n, CAS_n and WE_n. 11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)). 12. Maximum external load capacitance on ZQ pin: 5pF. 13. Only applicable if TEN pin does not have an internal pull-up. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits Current Specifications – Limits Table 8: x16 IDD, IPP, and IDDQ Current Limits – Rev. A DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 Symbol IDD0: One bank ACTIVATE-to-PRECHARGE current Unit Notes 2, 3, 4 110 120 130 TBD mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current 6 6 6 TBD mA IDD1: One bank ACTIVATE-to-READ-to-PRECHARGE current 140 150 160 TBD mA 3, 4, 5 IDD2N: Precharge standby current 90 100 110 TBD mA 4, 6, 7, 8, 9, 10, 11 IDD2NT: Precharge standby ODT current 110 120 130 TBD mA 4, 11 IDD2P: Precharge power-down current 50 60 70 TBD mA 4, 11 IDD2Q: Precharge quiet standby current 90 90 100 TBD mA 4, 11 IDD3N: Active standby current 110 110 120 TBD mA 4, 11 6 6 6 TBD mA IPP3N: Active standby IPP current IDD3P: Active power-down current 70 80 80 TBD mA 4, 11 IDD4R: Burst read current 300 300 350 TBD mA 4, 14, 13, 11 IDD4W: Burst write current 300 320 350 TBD mA 4, 11, 15, 16, 17, 18 IDD5R: Distributed refresh current (1X REF) 128 128 136 TBD mA 4, 19, 20 IPP5R: Distributed refresh IPP current (1X REF) 10 10 10 TBD mA IDD6N: Self refresh current; 0–85°C 60 60 60 TBD mA 11, 21 IDD6E: Self refresh current; 0–95°C 70 70 70 TBD mA 11, 22 IDD6R: Self refresh current; 0–45°C 50 50 50 TBD mA 11, 23, 24 IDD6A: Auto self refresh current (25°C) 40 40 40 TBD mA 11, 24 IDD6A: Auto self refresh current (45°C) 50 50 50 TBD mA 11, 24 IDD6A: Auto self refresh current (75°C) 70 70 70 TBD mA 11, 24 IPP6X: Auto self refresh current IPP current 10 10 10 TBD mA 11, 24 IDD7: Bank interleave read current 400 410 430 TBD mA 4 IPP7: Bank interleave read IPP current 30 30 30 TBD mA IDD8: Maximum power-down current 40 40 40 TBD mA Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1. 2. 3. 4. 11 DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. When additive latency is enabled for IDD0, current changes by approximately 0%. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. The IDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤ 85°C: 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits When TC < 0°C: IDD2P and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by+ 4%; and IDD7 must be derated by +11%. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by +3%; IDD2P must be derated by +40%. When additive latency is enabled for IDD1, current changes by approximately +4%. When additive latency is enabled for IDD2N, current changes by approximately 0%. When DLL is disabled for IDD2N, current changes by approximately –23%. When CAL is enabled for IDD2N, current changes by approximately –25%. When gear-down is enabled for IDD2N, current changes by approximately 0%. When CA parity is enabled for IDD2N, current changes by approximately +7%. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, IDD6x, and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. When additive latency is enabled for IDD3N, current changes by approximately +0.6%. When additive latency is enabled for IDD4R, current changes by approximately +5%. When read DBI is enabled for IDD4R, current changes by approximately 0%. When additive latency is enabled for IDD4W, current changes by approximately +4%. When write DBI is enabled for IDD4W, current changes by approximately 0%. When write CRC is enabled for IDD4W, current changes by approximately –3%. When CA parity is enabled for IDD4W, current changes by approximately +12%. When 2X REF is enabled for IDD5R, current changes by approximately –14%. When 4X REF is enabled for IDD5R, current changes by approximately –33%. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0–85°C). Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0–95°C). Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0–45°C). IDD6R and IDD6A values are typical. Table 9: x16 IDD, IPP, and IDDQ Current Limits – Rev. B Symbol DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes IDD0: One bank ACTIVATE-to-PRECHARGE current 90 96 102 108 114 mA 2, 3, 4 IPP0: One bank ACTIVATE-to-PRECHARGE IPP current 6 6 6 6 6 mA IDD1: One bank ACTIVATE-toREAD-to-PRECHARGE current 114 120 126 132 138 mA 3, 4, 5 IDD2N: Precharge standby current 66 68 70 72 74 mA 4, 6, 7, 8, 9, 10, 11 IDD2NT: Precharge standby ODT current 90 100 100 110 120 mA 4, 11 IDD2P: Precharge power-down current 50 50 50 50 50 mA 4, 11 IDD2Q: Precharge quiet standby current 60 60 60 60 60 mA 4, 11 IDD3N: Active standby current 80 86 92 98 104 mA 4, 11 CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits Table 9: x16 IDD, IPP, and IDDQ Current Limits – Rev. B (Continued) DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Symbol Unit Notes IPP3N: Active standby IPP current 6 6 6 6 6 mA IDD3P: Active power-down current 70 74 78 82 86 mA 4, 11 IDD4R: Burst read current 250 270 292 314 336 mA 4, 14, 13, 11 IDD4W: Burst write current 230 246 264 282 300 mA 4, 11, 15, 16, 17, 18 IDD5R: Distributed refresh current (1X REF) 100 106 112 118 124 mA 4, 19, 20 IPP5R: Distributed refresh IPP current (1X REF) 10 10 10 10 10 mA IDD6N: Self refresh current; 0–85°C 60 60 60 60 60 mA IDD6E: Self refresh current; 0–95°C 70 70 70 70 70 mA 11, 22 IDD6R: Self refresh current; 0–45°C 40 40 40 40 40 mA 11, 23, 24 IDD6A: Auto self refresh current (25°C) 17.2 17.2 17.2 17.2 17.2 mA 11, 24 IDD6A: Auto self refresh current (45°C) 40 40 40 40 40 mA 11, 24 IDD6A: Auto self refresh current (75°C) 60 60 60 60 60 mA 11, 24 IPP6X: Auto self refresh current IPP current 10 10 10 10 10 mA 11, 24 IDD7: Bank interleave read current 340 350 360 370 380 mA 4 IPP7: Bank interleave read IPP current 30 30 30 30 30 mA IDD8: Maximum power-down current 50 50 50 50 50 mA Notes: 1. 2. 3. 4. 11, 21 11 DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. When additive latency is enabled for IDD0, current changes by approximately 0%. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. The IDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤ 85°C: When TC < 0°C: IDD2P and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by +4%; and IDD7 must be derated by +11%. 5. 6. 7. 8. 9. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by +3%; IDD2P must be derated by +40%. When additive latency is enabled for IDD1, current changes by approximately +4%. When additive latency is enabled for IDD2N, current changes by approximately 0%. When DLL is disabled for IDD2N, current changes by approximately –23%. When CAL is enabled for IDD2N, current changes by approximately –25%. When gear-down is enabled for IDD2N, current changes by approximately 0%. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits 10. When CA parity is enabled for IDD2N, current changes by approximately +7%. 11. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, IDD6x, and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 12. When additive latency is enabled for IDD3N, current changes by approximately +0.6%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +4%. 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately –3%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately –14%. 20. When 4X REF is enabled for IDD5R, current changes by approximately –33%. 21. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0–85°C). 22. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0–95°C). 23. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0–45°C). 24. IDD6R and IDD6A values are typical. Table 10: x16 IDD, IPP, and IDDQ Current Limits – Rev. D Symbol DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes 2, 3, 4 IDD0: One bank ACTIVATE-toPRECHARGE current 90 96 102 108 114 mA IPP0: One bank ACTIVATE-toPRECHARGE IPP current 6 6 6 6 6 mA IDD1: One bank ACTIVATE-toREAD-to-PRECHARGE current 114 120 126 132 138 mA 3, 4, 5 IDD2N: Precharge standby current 66 68 70 72 74 mA 4, 6, 7, 8, 9, 10, 11 IDD2NT: Precharge standby ODT current 90 100 100 110 120 mA 4, 11 IDD2P: Precharge power-down current 50 50 50 50 50 mA 4, 11 IDD2Q: Precharge quiet standby current 60 60 60 60 60 mA 4, 11 IDD3N: Active standby current 90 96 102 108 112 mA 4, 11 IPP3N: Active standby IPP current 6 6 6 6 6 mA IDD3P: Active power-down current 70 74 78 82 86 mA 4, 11 IDD4R: Burst read current 250 270 292 314 336 mA 4, 14, 13, 11 IDD4W: Burst write current 250 264 284 300 320 mA 4, 11, 15, 16, 17, 18 CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits Table 10: x16 IDD, IPP, and IDDQ Current Limits – Rev. D (Continued) DDR4-21331 DDR4-2400 Symbol DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes IDD5R: Distributed refresh current (1X REF) 112 116 122 128 132 mA 4, 19, 20 IPP5R: Distributed refresh IPP current (1X REF) 10 10 10 10 10 mA IDD6N: Self refresh current; 0– 85°C 62 62 62 62 62 mA 11, 21 IDD6E: Self refresh current; 0– 95°C 72 72 72 72 72 mA 11, 22 IDD6R: Self refresh current; 0– 45°C 42 42 42 42 42 mA 11, 23, 24 IDD6A: Auto self refresh current (25°C) 17.2 17.2 17.2 17.2 17.2 mA 11, 24 IDD6A: Auto self refresh current (45°C) 42 42 42 42 42 mA 11, 24 IDD6A: Auto self refresh current (75°C) 62 62 62 62 62 mA 11, 24 IPP6X: Auto self refresh current IPP current 10 10 10 10 10 mA 11, 24 IDD7: Bank interleave read current 340 350 360 370 380 mA 4 IPP7: Bank interleave read IPP current 30 30 30 30 30 mA IDD8: Maximum power-down current 50 50 50 50 50 mA Notes: 1. 2. 3. 4. 11 DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. When additive latency is enabled for IDD0, current changes by approximately 0%. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. The IDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤ 85°C: When TC < 0°C: IDD2P and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by +4%; and IDD7 must be derated by +11%. 5. 6. 7. 8. 9. 10. 11. 12. 13. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by +3%; IDD2P must be derated by +40%. When additive latency is enabled for IDD1, current changes by approximately +4%. When additive latency is enabled for IDD2N, current changes by approximately 0%. When DLL is disabled for IDD2N, current changes by approximately –23%. When CAL is enabled for IDD2N, current changes by approximately –25%. When gear-down is enabled for IDD2N, current changes by approximately 0%. When CA parity is enabled for IDD2N, current changes by approximately +7%. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, IDD6x, and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. When additive latency is enabled for IDD3N, current changes by approximately +0.6%. When additive latency is enabled for IDD4R, current changes by approximately +5%. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits 14. 15. 16. 17. 18. 19. 20. 21. When read DBI is enabled for IDD4R, current changes by approximately 0%. When additive latency is enabled for IDD4W, current changes by approximately +4%. When write DBI is enabled for IDD4W, current changes by approximately 0%. When write CRC is enabled for IDD4W, current changes by approximately –3%. When CA parity is enabled for IDD4W, current changes by approximately +12%. When 2X REF is enabled for IDD5R, current changes by approximately –14%. When 4X REF is enabled for IDD5R, current changes by approximately –33%. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0–85°C). 22. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0–95°C). 23. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0–45°C). 24. IDD6R and IDD6A values are typical. Table 11: x16 IDD, IPP, and IDDQ Current Limits – Rev. E Symbol DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes 2, 3, 4 IDD0: One bank ACTIVATE-toPRECHARGE current 78 82 86 90 94 mA IPP0: One bank ACTIVATE-toPRECHARGE IPP current 6 6 6 6 6 mA IDD1: One bank ACTIVATE-toREAD-to-PRECHARGE current 110 114 118 122 126 mA 3, 4, 5 IDD2N: Precharge standby current 58 60 62 64 66 mA 4, 6, 7, 8, 9, 10, 11 IDD2NT: Precharge standby ODT current 72 76 80 84 88 mA 4, 11 IDD2P: Precharge power-down current 44 44 44 44 44 mA 4, 11 IDD2Q: Precharge quiet standby current 52 52 52 52 52 mA 4, 11 IDD3N: Active standby current 70 74 78 82 86 mA 4, 11 IPP3N: Active standby IPP current 6 6 6 6 6 mA IDD3P: Active power-down current 58 60 62 64 66 mA 4, 11 IDD4R: Burst read current 270 290 312 334 356 mA 4, 14, 13, 11 IDD4W: Burst write current 228 246 264 282 300 mA 4, 11, 15, 16, 17, 18 IDD5R: Distributed refresh current (1X REF) 92 94 96 98 100 mA 4, 19, 20 IPP5R: Distributed refresh IPP current (1X REF) 10 10 10 10 10 mA IDD6N: Self refresh current; 0– 85°C 68 68 68 68 68 mA CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 18 11, 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits Table 11: x16 IDD, IPP, and IDDQ Current Limits – Rev. E (Continued) DDR4-21331 DDR4-2400 DDR4-2666 DDR4-2933 Symbol DDR4-3200 Unit Notes IDD6E: Self refresh current; 0– 95°C 116 116 116 116 116 mA 11, 22 IDD6R: Self refresh current; 0– 45°C 42 42 42 42 42 mA 11, 23, 24 IDD6A: Auto self refresh current (25°C) 17.2 17.2 17.2 17.2 17.2 mA 11, 24 IDD6A: Auto self refresh current (45°C) 42 42 42 42 42 mA 11, 24 IDD6A: Auto self refresh current (75°C) 62 62 62 62 62 mA 11, 24 IPP6X: Auto self refresh current IPP current 10 10 10 10 10 mA 11, 24 IDD7: Bank interleave read current 340 350 360 370 380 mA 4 IPP7: Bank interleave read IPP current 26 26 26 26 26 mA IDD8: Maximum power-down current 36 36 36 36 36 mA Notes: 1. 2. 3. 4. 11 DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. When additive latency is enabled for IDD0, current changes by approximately +1%. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. The IDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤ 85°C: When TC < 0°C: IDD2P and IDD3P must be derated by +6%; IDD4R and IDD4W must be derated by +4%; and IDD7 must be derated by +11%. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by +3%; IDD2P must be derated by +10%. When additive latency is enabled for IDD1, current changes by approximately +8%. When additive latency is enabled for IDD2N, current changes by approximately +1%. When DLL is disabled for IDD2N, current changes by approximately –6%. When CAL is enabled for IDD2N, current changes by approximately –30%. When gear-down is enabled for IDD2N, current changes by approximately 0%. When CA parity is enabled for IDD2N, current changes by approximately +10%. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, IDD6x, and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. When additive latency is enabled for IDD3N, current changes by approximately +1%. When additive latency is enabled for IDD4R, current changes by approximately +4%. When read DBI is enabled for IDD4R, current changes by approximately -14%. When additive latency is enabled for IDD4W, current changes by approximately +3%. When write DBI is enabled for IDD4W, current changes by approximately 0%. When write CRC is enabled for IDD4W, current changes by approximately +5%. When CA parity is enabled for IDD4W, current changes by approximately +12%. When 2X REF is enabled for IDD5R, current changes by approximately –25%. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Current Specifications – Limits 20. When 4X REF is enabled for IDD5R, current changes by approximately –35%. 21. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0–85°C). 22. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0–95°C). 23. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0–45°C). 24. IDD6R and IDD6A values are typical. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Package Dimensions Package Dimensions Figure 5: 96-Ball FBGA Die Rev. A (package code HBA) Seating plane A 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. 0.12 A Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 14 ±0.1 12 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.34 ±0.05 9.5 ±0.1 Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Package Dimensions Figure 6: 96-Ball FBGA Die Rev. B (package code WBU) Seating plane A 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. 0.12 A Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 14 ±0.1 12 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.34 ±0.05 8 ±0.1 Notes: CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16Gb: x16 TwinDie Single Rank DDR4 SDRAM Package Dimensions Figure 7: 96-Ball FBGA Die Rev. E (package code KNR) Seating plane A 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. 0.12 A Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 13.5 ±0.1 12 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 0.34 ±0.05 6.4 CTR 7.5 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. CCMTD-1725822587-9947 16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.